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ICD2053B
Programmable Clock Generator
Features
* Clock outputs ranging from 391 kHz to 100 MHz (TTL levels) or 90 MHz (CMOS levels) * 2-wire serial interface facilitates programmable output frequency * Phase-Locked Loop oscillator input derived from external reference clock (1 MHz to 25 MHz) or External Crystal (2 MHz to 24 MHz) * Three-State output control disables output for test purposes * Sophisticated internal loop filter requires no external components or manufacturing tweaks as commonly required with external filters * Low power consumption makes device ideal for powerand space-critical applications * 8-pin 150-mil packaging achieves minimum footprint for space-critical applications * 5V operation * High-speed CMOS technology
Functional Description
The ICD2053B Programmable Clock Generator offers a fully user-programmable phase-locked loop in a single 8-pin package. The output may be changed "on the fly" to any desired frequency value between 391 kHz and 100 MHz (90 MHz at CMOS levels). The ICD2053B is ideally suited for any design in which package size, power, and/or frequency programmability are important design issues. The ability to dynamically change the output frequency adds a whole new degree of freedom for the designer. Some examples of the uses for this device include: laptop computers, in which slowing the speed of operation can mean less power consumption; graphics board dot clocks to allow dynamic synchronization of different brands of monitors or display formats; on-board test strategies where the ability to skew a system's desired frequency (e.g., 10%) allows worst-case evaluation.
Logic Block Diagram
Pin Configuration
Top View
XTALOUT SCLK GND DATA 1 2 3 4 8 7 6 5 2053b-1 XTALIN MUXREF/OE VDD CLKOUT
XTALIN XTALOUT
REFERENCE OSCILLATOR
/Q
f(REF) f OUT PLL /2N
MUX
CLKOUT
/2P
f OUT
7
7
5
3
SCLK DATA MUXREF/OE
2053b-2
CONTROL LOGIC
V DD
GND
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
* CA 95134 * 408-943-2600 August 1994 - Revised October 1995
ICD2053B
Pin Summary
Name XTALOUT SCLK GND DATA CLKOUT VDD MUXREF/OE
[1, 2]
Number 1 2 3 4 5 6 7
Description Reference crystal feedback Serial clock input line for programming purposes Ground Serial data input line for programming purposes Programmable clock output. This clock output can be three-stated by either pin 7, when it is configured as an Output Enable pin, or by bit 1 of the Control register. +5 volts If bit 3 (Pin 7 Usage) in the Control register is set to 1, this input pin controls the multiplexed reference frequency function. The operation is defined in Table 1. If bit 3 (Pin 7 Usage) in the Control Register is set to 0, this input pin controls the three-state output function. The operation is defined in Table 1. On power-up, pin 7 implements the OE function; a HIGH on pin 7 enables CLKOUT. An internal pull-up allows pin to be not-connected. Reference crystal input or external reference input (f(REF)) All serial words are shifted in bit-serially starting with the LSB. A low-to-high transition on SCLK is used to shift data. Whenever the Protocol word is detected, the preceding 8 bits are transferred into the Control register. The control command is then immediately executed. Control Register The Control register is used to control the non-frequency setting aspects of the ICD2053B. It is an 8-bit register, which is defined as shown in Figure 1 and Table 1. At power-up, the Control register is loaded with 0000 0100. This means that the MUXREF Control bit is set to 1, forcing the CLKOUT to equal the reference frequency. The Program register is disabled from loading. The "OE Control" and "Pin 7 Usage" bits are set to 0, implying that pin 7 is an output enable pin. 3 Pin 7 Usage 2 MUXREF Control 1 OE Control 0 Enable Program Word
XTALIN[1, 2]
8
ICD2053B Registers
The ICD2053B contains two registers, Control and Program. These registers are written using a protocol which uses a Protocol word = 011110 to distinguish Control register data from Program register data. This Protocol word is recognized by the four sequential 1s; therefore, all other data sent must have a 0 bit stuffed in after each sequence of three sequential 1s (whether originally followed by a 1 or a 0). This is called bit-stuffing. Please see the example under "Program Register Example" and the "Frequency Modification Procedure" section. Following is a bit-stuffing example (read right to left, LSB to MSB): To send this programming data: 1111 0111 1110 111111 Transmit this serial bit stream: 10111 00111 01110 01110111 7 0 (Reserved) 6 0 (Reserved) 5 Duty Cycle Adjust (Set to 1) 4 0 (Reserved)
Figure 1. Control Register
Notes: 1. For best accuracy, use a parallel-resonant crystal. 2. Assume CLOAD 17 pF.
2
ICD2053B
Table 1. Control Register Bit RESERVED Duty Cycle Adjust Pin 7 Usage Definition For future use. Set to 0. Set to 1 to reduce duty cycle by approximately 0.7 ns. Normally set to 1. Definition of whether pin 7 is MUXREF or OE input pin 0 = Pin 7 is OE input (default) 1 = Pin 7 is MUXREF input Allows internal control of MUXREF. If enabled, this feature automatically multiplexes the reference frequency to the CLKOUT output. This is used to change output glitch-free to new frequencies. 0 = CLKOUT is VCO frequency 1 = CLKOUT is f(REF) (default) Forces the CLKOUT output into a three-state mode 0 = CLKOUT is VCO frequency or f(REF) (default) (depending on current MUXREF state) 1 = CLKOUT is three-stated Enable Program word loading into Program register. When enabled, the Program word may be shifted in. This permits changing the Control register without disturbing Program register data. 0 = Program register is disabled from loading (default) 1 = Program register is enabled to receive data Mux Field (M) M 000 001 010 Notes MSB (Most Significant Bits) Set to logic 1 to increase duty cycle by approx. 0.7 ns. Normally set to 1. 011 100 101 110 111 Divisor 1 2 4 8 16 32 64 128
MUXREF Control
OE Control
Enable Program Word
Program Register The Program register can be loaded with a 22-bit programming word, the fields of which are defined in Table 2. Table 2. Program Register Field P Counter value (P') Duty Cycle Adjust Up (D) Mux (M) Q Counter value (Q') Index (I) # of Bits 7 1
3 7 4 LSB (Least Significant Bits)
The VCO frequency, f (VCO), is determined by the following relation: f(VCO) = (2 * f(REF) * P/Q) where P' = P - 3 Q' = Q - 2 f(REF) = Reference frequency (1 MHz to 25 MHz)
The index field (I) is used to preset the VCO to an appropriate range. The value for this field should be chosen from the following table. (Note that this table is referenced to the VCO frequency f(VCO) rather than to the desired output frequency and that only the MSB is significant.) Index Field (I) I 0000 1000 f(VCO) @ 5V 50 to 80 MHz 80 to 150 MHz
The value of f(VCO) must remain between 50 MHz and 150 MHz. Therefore, for output frequencies below 50 MHz, f(VCO) must be brought into range. To accomplish this, a post-VCO Divisor is selected by setting the values of the Mux field (M) as follows:
To assist with these calculations, Cypress/IC Designs provides the BITCALC program. BITCALC is a WindowsTM program for the IBM PC which automatically generates the appropriate programming word from the user's reference input and desired output frequencies.
3
ICD2053B
VCO Programming Constraints
There are seven primary programming constraints the user must be aware of:
.
Output Frequency Accuracy
The accuracy of the ICD2053B output frequency depends on the target output frequency and reference frequency. As stated previously, the output frequency of the ICD2053B is mathematically related to the input reference frequency: f(OUT) = (2 * f(REF) * P/Q) / 2n, n = 0...7. Only certain output frequencies are possible for a particular reference frequency. However, the ICD2053B generally produces an output frequency within 0.1% of the desired output frequency. Specifics regarding accuracy (in ppm) are given for any desired output frequency in the BITCALC program output.
Table 3. Programming Constraints Parameter f(REF) f(REF)/Q f(VCO) divisor fOUT Q P Minimum 1 MHz 200 kHz 50 MHz 1 50 MHz/128 3 4 Maximum 25 MHz 1 MHz 150 MHz 128 100 MHz 129 130
Frequency Modification Procedure
When changing to a new frequency, there is a period of time during which the output signal will jump in frequency, or glitch due to changes in the serial word. For applications in which it is critical that the output clock not glitch and always maintain some known value, the MUXREF feature in the Control register should be used. MUXREF causes the reference clock to be multiplexed, glitch-free, to the output clock. The output will remain at this fixed frequency while the VCO seeks its new programmed value. The procedure for programming the ICD2053B to an initial or new frequency is as follows: 1. Load the Control register to enable MUXREF and enable loading of the Program register. This will set the output to the reference frequency. The transition is guaranteed to be glitch-free. (See timing specifications.) Note that the Protocol Word must follow the Control register data. Also note that all data is shifted in LSB (Least Significant Bit) first. Control word = 0 1 1 1 1 0 0 0 0 0 X 1 0 1 LSB Protocol Word Control Reg. Data The state of the Pin 7 Usage bit is defined by the user, and so is denoted as X. 2. Shift in the desired output frequency value computed via a 22-bit data word (as defined above), plus any bit-stuffs (as defined above). Remember to bit-stuff a 0 after any three sequential 1s. 3. Load the Control register to enable MUXREF and disable loading of the Program register. This loads the Program word bits into the Program register and keeps the output set to the reference frequency while the new frequency settles Control word = 0 1 1 1 1 0 Protocol Word 0000 X100 Control Reg. Data
The constraints have to do with trade-offs between optimum speed with lowest noise, VCO stability and factors affecting the loop equation. The factors are listed for completeness sake; however, by using the above-mentioned BITCALC program, these constraints become transparent.
PROGRAM Register Example
The following is an example of the calculations BITCALC performs: Derive the proper programming word for a 39.5 MHz output frequency, using 14.31818 MHz as the reference frequency: Since 39.5 MHz < 50 MHz, double it to 79.0 MHz. Set M to 001 to post divide by 2. Set I to 0000. The result: f(VCO) = 79.0 = (2 * 14.31818 * P/Q)
P
/Q = 2.7587
Several choices of P and Q are available for this example: P 69 80 91 Q 25 29 33 f(VCO) 79.0363 78.9969 78.9969 Error (PPM) 460 40 419
Normally, one would choose (P,Q) = (80,29) for the best accuracy (40 PPM). However, we will choose (P,Q) = (91,33) as it illustrates bit stuffing. Therefore: P' = P - 3 = 91 - 3 = 88 = 1011000 Q' = Q - 2 = 33 - 2 = 31 = 0011111 The programming word, W, is generated by first creating the non-bit-stuffed word W' by concatenating P'=1011000, D=1, M=001, Q'=0011111, I=0000, and then bit-stuffing. W' = 1011000 1 001 0011111 0000 W = 10110001001001101110000 Zeros were stuffed in one place in this example.
4. Wait for VCO to settle in the new state (10 ms to within 0.1% of the new frequency). Load the Control register to enable new frequency output. The transition is guaranteed to be glitch-free. (See the timing specifications.) Control word = 0 1 1 1 1 0 Protocol Word 0000 X000 Control Reg. Data
4
ICD2053B
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Supply Voltage to Ground Potential .................-0.5V to +7.0V Input Voltage ................................................... -0.5V to VDD+0.5 Operating Temperature ......................................0C to +70C Storage Temperature ....................................... -65C to +150C Max. Soldering Temperature (10 sec) ..................... +260C Junction Temperature ............................................... +125C Static Discharge Voltage .........................................Class 1[3] (per MIL-STD-883, Method 3015)
Operating Range
Range Commercial
Note: 3. Static sensitive <2000V.
Ambient Temperature 0C to +70C
VDD 5V 10%
Operating Conditions
Parameter VDD TA CL Supply Voltage Ambient Operating Temperature Load Capacitance Description Min. 4.5 0 Max. 5.5 70 25 Unit V C pF
Electrical Characteristics Over the Operating Range
Parameter VOH VOL VIH VIL VIH VIL IIH IIL IIH IIL IOZ IDD Description HIGH-level Output Voltage LOW-level Output Voltage HIGH-level Input Voltage LOW-level Input Voltage HIGH-level Reference Input Voltage, when DC coupled[4] LOW-level Reference Input Voltage, when DC coupled[4] Input HIGH Current Input LOW Current Input HIGH Current Input LOW Current Output Leakage Current Power Supply Current Test Conditions IOH = -4.0 mA IOL = 4.0 mA Except XTALIN pins Except XTALIN pins XTALIN pin only XTALIN pin only VIN = 5.0V, except SCLK VIN = 0.5V, except SCLK VIN = 5.0V, SCLK only VIN = 0.5V, SCLK only Three-state VDD=VDD max., 100 MHz, VIN=VDD or 0V 13 VDD-0.8 0.8 100 -250 250 -100 10 50 2.0 0.8 Min. 2.4 0.4 Max. Unit V V V V V V A A A A A mA
Capacitance
Parameter CIN CIN Description Input Capacitance, except XTALIN pin Input Capacitance, XTALIN pin Max. 10 34 Unit pF pF
Switching Characteristics Over the Operating Range
Parameter f(REF) t(REF) t1 Name Reference Frequency Reference Clock Period Reference Clock HIGH Time t(REF) = 1/f(REF) Input pulse width HIGH for reference. Measured at VDD/2, DC coupled.[4] Description Reference Oscillator nominal value
[4]
Min. 1 40 16
Max. 25 1000
Unit MHz ns ns
Note: 4. See Externally Driven Crystal Oscillator section of the "Crystal Oscillator Topics" Application Note. For AC coupling, use an input duty cycle near 50%.
5
ICD2053B
Switching Characteristics Over the Operating Range (continued)
Parameter t2 Name Output Period Description CLKOUT period (frequency), TTL levels CLKOUT period (frequency), CMOS levels t3 Output Duty Cycle (t0/t2) Duty cycle of CLKOUT measured at 1.4V (TTL) threshold Duty cycle of CLKOUT measured at VDD/2 (CMOS) threshold t4 Rise Time Rise time for the clock output into a 25 pF load Fall time for the clock output into a 25 pF load f(OUT) < 50 MHz AND post-divide > 2 f(OUT) > 50 MHz OR post-divide = 1 post-divide > 2 post-divide = 1 TTL 0.4V to 2.4V CMOS, 0.1VDD to 0.9VDD TTL 0.4V to 2.4V CMOS, 0.1VDD to 0.9VDD 450 t(REF) 15 0 0 t13 t16 - 10 t1 - 10 0 tnew/2 18 t(REF)/10 0 0 20 20 told + 25 t(REF) + 25 t16 + 10 t1 + 10 t(REF) + 25 tnew * 3/2 + 25 3 * t(REF) + 25 Min. 10 (100 MHz) 11.1 (90 MHz) 45% 40% 45% 40% Max. 2560 (391 kHz) 2560 (391 kHz) 55% 60% 55% 60% 3 6 3 6 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit ns
t5
Fall Time
t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 told tnew tlock t20
SCLK HIGH Time Clock Valid Serial Data Set-up Hold
Minimum HIGH time for the SCLK clock Time required for the CLKOUT oscillator to become valid after last SCLK clock[5] Time required for the data to be valid prior to the rising edge of SCLK Time required for the data to remain valid after the rising edge of SCLK
Delay, MUXREF[6] Asserted Time for CLKOUT to go HIGH after assertion of to CLKOUT HIGH MUXREF [6] Transition, f(OLD) to f(REF) Reference Output High Time Reference Output Low Time Transition, f(REF) to f(NEW) Transition, MUXREF[6] released to CLKOUT LOW Delay of first falling edge of f(REF) signal at output Output during MUXREF[6], reference DC coupled Output during MUXREF[6], reference DC coupled Time for CLKOUT to go HIGH after release of MUXREF [6] Delay of first falling edge of f(NEW) signal at output
Reference Clock Low Time Input pulse width low for reference. Measured at VDD/2, DC coupled[4] Reference Input Rise/Fall Output Enable Delay Output Disable Delay Original Period New Period VCO Lock Time SCLK LOW Time Rise/fall time for DC coupled reference input[4] Delay from Output Enable HIGH to Output Valid Delay from Output Enable LOW to Output Floating Output period before reprogramming, 1/f(OLD) Output period after reprogramming, 1/f(NEW) Time for VCO to lock onto new f(VCO) within 0.1% Minimum LOW time for the SCLK clock
10 450
msec ns
Notes: 5. This is the time for the serial word shifted in to take effect, including the Control Word output enable bit. The VCO stabilization time is separate. 6. Pin or internal bit.
6
ICD2053B
Switching Waveforms
Rise and Fall Times
t (REF) f (REF) VDD/2 t1 t2 t0 CLKOUT t4 t5 VOH VOL
2053b-3
t16 t 17
VDD-0.8V 0.8V t 17
Serial Programming Timing
t6 SCLK t7 CLKOUT t8 DATA t9 CLKOUT VALID t 20
DATA VALID
2053b-4
MUXREF Timing [7]
MUXREF (pin) t15 t10 CLKOUT told
ORIGINAL FREQUENCY
t 11
t13
t 12
t14
t (REF)
REFERENCE FREQUENCY
t new
REVISED FREQUENCY
2053b-5
Three-State Timing
THREE-STATE (pin or internal) t 18 t 19
CLKOUT
CLKOUT VALID
2053b-6
Note: 7. Identical behavior is exhibited when the internal MUXREF bit in the Control register is HIGH.
7
ICD2053B
Ordering Information
Ordering Code ICD2053BSC-1 Document #: 38-00412-A Windows is a trademark of Microsoft Corporation. Package Name S8 Package Type 8-Pin (150-Mil) SOIC Operating Range
Package Diagrams
8-Lead (150-Mil) SOIC S8
(c) Cypress Semiconductor Corporation, 1996. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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